Christopher Batten Research Group

Cornell University

How can programmable accelerators and chip-level interconnection networks be designed to improve performance and energy efficiency of future computer systems? The research group builds prototype systems and tape-out class projects that implement digital ASIC accelerators and mixed digital/analog chips to validate design assumptions and test hardware-software integration. Researchers develop parallel programming frameworks and software-managed scratchpad memory techniques to support dynamic task parallelism and efficient use of manycore architectures. The group explores productive VLSI chip design methodologies and generator-checking techniques for dynamic hardware description languages to improve reliability and correctness of hardware generators. The lab evaluates programmable accelerator architectures and eFPGA integration for cache-coherent SoCs to study scalable accelerator-software interfaces.