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Işıl Dillig Research Group
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Request a correction or removal ↗ How can automatic program synthesis and verification make software safer and easier to build? Dillig's research develops program synthesis algorithms that generate code from specifications and examples to automate routine programming tasks. The group builds program verification and automated logical reasoning techniques to prove absence of classes of errors and security vulnerabilities. Researchers design domain-specific languages and type systems and apply automated theorem proving to scale verification and synthesis tools. The lab pursues interdisciplinary projects linking program analysis with AI, databases, security, and systems.
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